1. Technical Field
The present invention relates to frequency divider circuits in general, and in particular, to non-integer frequency divider circuits. Still more particularly, the present invention relates to a programmable non-integer frequency divider circuit.
2. Description of the Related Art
Frequency divider circuits are commonly employed in electronic devices that include counting circuits, phase-locked loop circuits, and/or frequency synthesizer circuits. Generally speaking, frequency dividers are used to generate signals of relatively lower frequencies by dividing a high frequency signal already existed within an electronic system. For example, if a 50 MHz signal is desired from a 100 MHz clock signal existed within an electronic system, a frequency divider is used to divide the 100 MHz clock signal by two.
Due to the nature of digital logic, the easiest frequency divider circuits to design are those that divide the frequency of an input signal by a factor of 2n, where n is an integer. These group of frequency divider circuits can divide an input clock frequency by 2, 4, 8, 16, etc. In other words, these group of frequency divider circuits can produce an output cycle for every 2, 4, 8, 16, etc. input cycles, respectively. More sophisticated frequency divider circuits that are capable of dividing an input signal by all integer values, such as 2, 3, 4, 5, etc., have been developed. But recently, it has become necessary to have frequency divider circuits that is capable of dividing an input signal by non-integer values; that is, ones that can produce an output cycle for every, for example, 2.5 or 3.25 input cycles.
The present disclosure describes a method for constructing a programmable non-integer frequency divider circuit with a desired range and resolution.